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_______________________________________________________________ maxim integrated products 1 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com. integrated charger, dual main step-down controllers, and dual ldo regulators MAX17085B general description the MAX17085B is an all-in-one notebook power solution integrating a multichemistry battery charger, dual fixed- output quick-pwm k step-down controllers, and dual keep-alive linear regulators: charger: the high-frequency (~1.4mhz) multichem - istry battery charger uses a current-mode, fixed inductor current ripple architecture that significantly reduces component size and cost. low-offset sense amplifiers allow the use of low-value sense resistors for charging and input current limit. the charger uses n-channel switching mosfets. adjustable charge current, charge voltage, and cell selection allow for flexible use with different battery packs. charge current is set by an analog control input, or a pwm input. high-accuracy current-sense ampli - fiers provide fast cycle-by-cycle current-mode control to protect against short circuits to the battery and respond quickly to system load transients. additionally, the char - ger provides a high-accuracy analog output that is pro - portional to the adapter current. an integrated charge pump controls an n-channel adapter selector switch. the charge pump remains active even when the charger is off. when the adapter is absent, a p-channel mosfet selects the battery. main smps: the dual quick-pwm step-down con - trollers with synchronous rectification generate the 5v and 3.3v main power in a notebook. low- side mosfet sensing provides a simple low-cost, highly efficient valley current-limit protection. the MAX17085B also includes output undervoltage, out - put overvoltage, and thermal-fault protection. separate enable inputs for each smps and a com - bined open-drain power-good output allow flex - ible power sequencing. voltage soft-start reduces inrush current, while passive shutdown discharges the output through an internal switch. fast transient response, with an extended on-time feature reduces output capacitance requirements. selectable pulse- skipping mode and ultrasonic mode improve light- load efficiency. ultrasonic mode operation maintains a minimum switching frequency at light loads, mini - mizing audible noise effects. dual ldo regulators: an internal 5v/100ma ldo5 with switchover can be used to either generate the 5v bias needed for power-up or other lower power always-on suspend supplies. another 3.3v/50ma ldo3 provides always-on power to a system microcontroller. features s all-in-one charger plus dual main step-down controllers s 5v/100ma and 3.3v/50ma ldo regulators s main dual quick-pwm with fast transient response and extended on-time 300khz to 800khz switching frequency fixed 5v and 3.3v smps outputs low-noise ultrasonic mode autoretry fault protection s charger high switching frequency (1.4mhz) selectable 2-, 3-, and 4-cell battery voltage automatic selection of system power source internal charge-pump for adapter n-channel mosfets drive q 0.4% accurate charge voltage q 2.5% accurate input current limiting q 3% accurate charge current s monitor outputs for ac adapter current ( q 2% accuracy) battery discharge current ( q 2% accuracy) ac adapter ok s analog/pwm (100hz to 500khz) adjustable charge current setting s ac adapter overvoltage and overcurrent protection applications notebook computers pdas and mobile communicators 5v and 3.3v supplies 2-to-4, li+-cell, battery-powered devices 19-5135; rev 0; 1/10 ordering information + denotes a lead(pb)-free /rohs-compliant package. *ep = exposed pad. pin configuration appears at end of data sheet. quick-pwm is a trademark of maxim integrated products, inc. evaluation kit available part temp range pin-package MAX17085B etl+ -40c to +85c 40 tqfn-ep*
integrated charger, dual main step-down controllers, and dual ldo regulators MAX17085B 2 ______________________________________________________________________________________ stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. ton, dcin, cssp, batt, csip to gnd, lx_ to gnd ........................................................ -0.3v to +28v csip to csin, cssp to cssn .............................. -0.3v to +0.3v ldo3, ldo5, vcc to gnd (note 2) ....................... -0.3v to +6v iset, vctl, acin, acok to gnd .......................... -0.3v to +6v out3, out5 to gnd (note 2) ................................ -0.3v to +6v on3, on5, pgood to gnd ................................... -0.3v to +6v ilim3, ilim5, skip, ref to gnd .............. -0.3v to (v cc + 0.3v) gnd to ep ............................................................ -0.3v to +0.3v dl_ to ep ............................................... -0.3v to (v ldo5 + 0.3v) bst_ to gnd ......................................................... -0.3v to +34v bst_ to ldo5 ........................................................ -0.3v to +28v dh3 to lx3 ............................................ -0.3v to (v bst3 + 0.3v) bst3 to lx3 ............................................................. -0.3v to +6v dh5 to lx5 ............................................ -0.3v to (v bst5 + 0.3v) bst5 to lx5 ............................................................. -0.3v to +6v dhc to lxc ........................................... -0.3v to (v bstc + 0.3v) pdsl to gnd ....................................................... -0.3v to + 36v bstc to lxc ........................................................... -0.3v to +6v cells, cc, iinp to gnd ...................... -0.3v to (v ldo5 + 0.3v) ldo_ short circuit to gnd ....................................... momentary ldo5 current (internal regulator) continuous ............. +100ma ldo3 current (internal regulator) continuous ............... +50ma ldo_ current (switched over) continuous .................. +200ma continuous power dissipation (t a = +70 n c) 40-pin thin qfn (derate 34.5mw/ n c above +70 n c) 2857mw operating temperature range .......................... -40 n c to +85 n c junction temperature ..................................................... +150 n c storage temperature range ............................ -65 n c to +150 n c soldering temperature (reflow) ...................................... +240 n c electrical characteristics (circuit of figure 1, no load on ldo5, ldo3, out5, out3, and ref, v cc = 5v, on3 = on5 = v cc , v dcin = v lxc = v cssp = v cssn = 19v, v bstc - v lxc = 5v, v batt = v csip = v csin = 12.6v, v vctl = v iset = 1.8v, cells = open, t a = 0c to +85c , unless oth - erwise noted. typical values are at t a = +25c.) absolute maximum ratings (note 1) note 1: absolute maximum ratings valid using 20mhz bandwidth limit. note 2: ldo5 has a weak leakage to v cc when ldo5 is more than 0.5v above v cc . out5 has a weak leakage to v cc when out5 is more than 0.5v above v cc . parameter symbol conditions min typ max units input supplies adapter present quiescent current i dcin + i cssp + i cssn , on3 = on5 = skip = v cc , v out3 = 3.5v, v out5 = 5.3v charging enabled 3 6 ma charging disabled 1.5 2.5 adapter absent quiescent current i dcin + i cssp + i cssn , on3 = on5 = skip = v cc , v out3 = 3.5v, v out5 = 5.3v v iset = 2.4v, iinp on 1.5 2.5 ma v iset = gnd 1.2 2.2 cssn input current v cssp = v cssn = 24v, t a = +25 c 0.1 2 f a batt + csip + csin + lxc input current v batt = 16.8v, adapter absent, t a = +25 c 4 f a v batt = 2v to 19v, adapter present 200 650 dcin input current i dcin on3 = on5 = skip = v cc , charger disabled; v out3 = 3.5v, v out5 = 5.3v 0.1 0.2 ma dcin standby supply current dcin = 5v to 24v, on3 = on5 = gnd 130 270 f a v cc supply current i cc on3 = on5 = skip = v cc , charger disabled; v out3 = 3.5v, v out5 = 5.3v 1.0 1.5 ma dcin input voltage range note: ldo5 is not guaranteed to be in regulation until dcin is above 6v. 4.5 24 v
integrated charger, dual main step-down controllers, and dual ldo regulators MAX17085B _______________________________________________________________________________________ 3 electrical characteristics (continued) (circuit of figure 1, no load on ldo5, ldo3, out5, out3, and ref, v cc = 5v, on3 = on5 = v cc , v dcin = v lxc = v cssp = v cssn = 19v, v bstc - v lxc = 5v, v batt = v csip = v csin = 12.6v, v vctl = v iset = 1.8v, cells = open, t a = 0c to +85c , unless oth - erwise noted. typical values are at t a = +25c.) parameter symbol conditions min typ max units dcin undervoltage-lockout trip point for charger v dcin(uvlo) v dcin falling 7.0 7.2 v v dcin rising 7.7 7.9 dcin por threshold v dcin(por) falling edge of dcin 2.0 v v cc undervoltage lockout threshold v cc(uvlo) falling edge of v cc , pwm disabled below this threshold 3.8 4.0 4.3 v rising edge of v cc 4.2 v cc por threshold falling edge of v cc 1.5 v linear regulators ldo_ output-voltage accuracy v ldo5 dcin = 6v to 24v, on5 = on3 = gnd 0ma < i ldo5 < 100ma, on5 = gnd 4.90 5.00 5.10 v v ldo3 ldo5 = 5v, i ldo5 = 0 0ma < i ldo3 < 50ma, on3 = gnd 3.23 3.30 3.37 internal ldo voltage after switchover v ldo5 not production tested 4.4 4.5 4.6 v v ldo3 not production tested 2.7 2.8 2.9 ldo3 short-circuit current ldo3 = gnd 50 130 ma ldo5 short-circuit current ldo5 = gnd 100 260 ma ldo5 bootstrap switch resistance ldo5 to out5, v out5 = 5v, i ldo5 = 50ma 1.0 2.5 i ldo3 bootstrap switch resistance ldo3 to out3, v out3 = 3.3v, i ldo3 = 50ma 1.5 3 i thermal-shutdown threshold t shdn hysteresis = 50 n c +160 n c reference ref output voltage v ref i ref = 50 f a 2.09 2.10 2.11 v ref undervoltage-lockout threshold v ref_uvlo ref falling 2.0 v main smps out5 output voltage accuracy v out5 in = 6v to 28v, skip = ref 5.033 5.083 5.135 v out3 output voltage accuracy v out3 in = 6v to 28v, skip = ref 3.267 3.300 3.333 v load regulation error either smps, skip = 2v, i load = 0 to 5a -0.1 % either smps, skip = gnd, i load = 0 to 5a -1.7 either smps, skip = v cc , i load = 0 to 5a -1.5 line regulation error either smps, in = 6v to 28v 0.005 %/v dh5 on-time t on5 in = 12v, v out5 = 5.0v (note 3) r ton = 549k i (300khz + 10%) 1073 1263 1452 ns r ton = 202k i (800khz + 10%) 402 473 545
integrated charger, dual main step-down controllers, and dual ldo regulators MAX17085B 4 ______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 1, no load on ldo5, ldo3, out5, out3, and ref, v cc = 5v, on3 = on5 = v cc , v dcin = v lxc = v cssp = v cssn = 19v, v bstc - v lxc = 5v, v batt = v csip = v csin = 12.6v, v vctl = v iset = 1.8v, cells = open, t a = 0c to +85c , unless oth - erwise noted. typical values are at t a = +25c.) parameter symbol conditions min typ max units dh3 on-time t on3 in = 12v, v out3 = 3.3v (note 3) r ton = 549k i (300khz - 10%) 866 1019 1171 ns r ton = 202k i (800khz - 10%) 325 382 439 minimum off-time t off(min) (note 3) 210 270 330 ns extended on-time blanking duty cycle > 50%; not for production test 300 360 ns soft-start time t ss rising edge on on_ 2 ms ultrasonic operating frequency f sw(usonic) skip = gnd 15 22 khz main smps fault detection out_ overvoltage trip threshold (pgood pulled low above this level) with respect to error comparator threshold 13 16 19 % out_overvoltage fault propagation delay t ovp fb_ forced 50mv above trip threshold 10 f s out_ undervoltage protection trip threshold with respect to error comparator threshold 65 70 75 % out_ output undervoltage fault propagation delay t uvp 10 f s pgood lower trip threshold with respect to error comparator threshold, falling edge, hysteresis = 15mv -350 -250 -150 mv pgood propagation delay t pgood out5 or out3 forced 50mv beyond pgood trip threshold, falling edge 10 f s pgood output low voltage pgood low impedance, on5 = on3 = gnd, i sink = 4ma 0.3 v pgood leakage current i pgood pgood high impedance, smps in regulation, pgood forced to 5.5v, t a = +25 c 1 f a fault reset timer 7 10 ms main smps current limit ilim_ adjustment range 0.2 2.1 v ilim_ leakage current t a = +25 c -0.1 +0.1 f a valley current-limit threshold (adjustable) v lim _ (val) v agnd - v lx _ v ilim _ = 0.5v 40 50 60 mv v ilim _ = 1.00v 87 100 113 v ilim _ = 2.10v 184 210 236 ultrasonic negative current-limit threshold i neg(us) 72 mv current-limit threshold (zero crossing) v zx v agnd - v lx _, skip = v cc or gnd, v ilim = 1v 1.5 mv
integrated charger, dual main step-down controllers, and dual ldo regulators MAX17085B _______________________________________________________________________________________ 5 electrical characteristics (continued) (circuit of figure 1, no load on ldo5, ldo3, out5, out3, and ref, v cc = 5v, on3 = on5 = v cc , v dcin = v lxc = v cssp = v cssn = 19v, v bstc - v lxc = 5v, v batt = v csip = v csin = 12.6v, v vctl = v iset = 1.8v, cells = open, t a = 0c to +85c , unless oth - erwise noted. typical values are at t a = +25c.) parameter symbol conditions min typ max units main smps inputs and outputs skip threshold voltage v skip high = skip 2.3 v cc v mid = pwm 1.5 1.9 low = ultrasonic 0 0.8 skip leakage current v skip = 0 or 5v, t a = +25 c -2 +2 f a on_ input logic levels high (smps on) 2.4 v low (smps off) 0.8 on_ leakage current v on3 = v on5 = 0 or 5v, t a = +25 c -2 +2 f a out_ discharge-mode on-resistance r dschg on_ = gnd 7.5 20 50 i smps gate drivers dh3, dh5 gate driver on-resistance r dh3 , r dh5 bst3 - lx3 and bst5 - lx5 forced to 5v; high state 1.6 3.8 i bst3 - lx3 and bst5 - lx5 forced to 5v; low state 1.6 3.8 dl3, dl5 gate driver on-resistance r dl3 , r dl5 dl3, dl5; high state 1.5 3.5 i dl3, dl5; low state 0.6 1.5 dh3, dh5 gate driver source/ sink current i dh dh3, dh5 forced to 2.5v, bst3 - lx3 and bst5 - lx5 forced to 5v 2 a dl3, dl5 gate driver source current i dl(source) dl3, dl5 forced to 2.5v 1.7 a dl3, dl5 gate driver sink current i dl(sink) dl3, dl5 forced to 2.5v 3.3 a dhc gate driver on- resistance r dhc high state, i dhc = 10ma 1.5 3 i low state, i dhc = -10ma 0.8 2.1 dlc gate driver on-resistance r dlc high state, i dlc = 10ma 3 6 i low state, i dlc = -10ma 3 6 internal bst_ switch on-resistance r bst i bst _ = 10ma, v dd = 5v 5 i bst_ leakage current i bst v bst _ = 24v, out3 and out5 above regulation threshold, t a = +25 c 2 20 f a charger smps dhc off-time k factor v dcin = 19v, v batt = 10v 30 35 40 ns/v sense voltage for minimum discontinuous mode ripple current v csip - v csin 5 mv zero crossing comparator threshold v csip - v csin 10 mv cycle-by-cycle current- limit sense voltage v csip - v csin 120 125 130 mv
integrated charger, dual main step-down controllers, and dual ldo regulators MAX17085B 6 ______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 1, no load on ldo5, ldo3, out5, out3, and ref, v cc = 5v, on3 = on5 = v cc , v dcin = v lxc = v cssp = v cssn = 19v, v bstc - v lxc = 5v, v batt = v csip = v csin = 12.6v, v vctl = v iset = 1.8v, cells = open, t a = 0c to +85c , unless oth - erwise noted. typical values are at t a = +25c.) parameter symbol conditions min typ max units charge-voltage regulation battery-regulation voltage accuracy v batt cells = open, vctl = ref, 2 cells -0.5 +0.5 % cells = gnd, vctl = ref, 3 cells -0.5 +0.5 cells = ldo3, vctl = ref, 4 cells -0.5 +0.5 vctl range cells = open, 2 cells 1.0 3.5 v vctl input bias current vctl = gnd or vctl = ref, t a = +25 c -1 +1 f a cells 3-cell threshold 0.8 v cells 2-cell level cells = open 1.9 2.1 2.3 v cells 4-cell threshold 2.8 v cells input bias current cells = gnd or cells = 3.6v, t a = +25 c -2 +2 f a charge-current regulation iset range charging current, analog setting 0 ref v full-charge-current accuracy (csip to csin) v csi v batt = 4v to 16.8v v iset = ref, or pwm = 100% 97 100 103 mv v iset = 0.6 x ref, or pwm = 60% 57.6 60.0 62.4 trickle charge-current accuracy v csi v batt = 4v to 16.8v, v iset = ref/36 or pwm = 2.7% 1.25 2.70 4.30 mv charge-current gain error -1.5 +1.5 % charge-current offset error based on v iset = ref and v iset = 0.6 x ref -1.4 +1.4 mv csip/csin/batt input-voltage range 0 24 v csip leakage current v csip = v csin = 24v, t a = +25 c -0.2 +0.2 f a csin leakage current v csip = v csin = 24v, t a = +25 c 1 4 f a iset power-down mode threshold v iset-sdn iset falling 20 26 32 mv iset rising 32 38 46 iset input bias current v iset = ref/2 and v iset = ref, t a = +25 c -0.15 +0.15 f a iset pwm threshold iset rising 2.4 v iset falling 0.8 iset frequency f iset 0.128 500 khz iset effective resolution f iset = 100khz 8 bit input source-current regulation input source current-limit threshold v css v cssp - v cssn 58.5 60.0 61.5 mv -2.5 +2.5 % cssp/cssn input-voltage range 5 26 v
integrated charger, dual main step-down controllers, and dual ldo regulators MAX17085B _______________________________________________________________________________________ 7 electrical characteristics (continued) (circuit of figure 1, no load on ldo5, ldo3, out5, out3, and ref, v cc = 5v, on3 = on5 = v cc , v dcin = v lxc = v cssp = v cssn = 19v, v bstc - v lxc = 5v, v batt = v csip = v csin = 12.6v, v vctl = v iset = 1.8v, cells = open, t a = 0c to +85c , unless oth - erwise noted. typical values are at t a = +25c.) parameter symbol conditions min typ max units iinp current-sense amplifier voltage gain g iinp 59.1 60.0 60.9 v/v iinp output-voltage range 0 4 v iinp accuracy v cssp - v cssn = 60mv -2 +2 % v cssp - v cssn = 40mv -3 +3 v cssp - v cssn = 20mv -4 +4 iinp gain error measured at v cssp - v cssn = 60mv and v cssp - v cssn = 20mv -1.25 +1.25 % iinp offset error measured at v cssp - v cssn = 60mv and v cssp - v cssn = 20mv -0.6 +0.6 mv adapter overcurrent (acoc) detection acocp threshold v csin-ocp with respect to v cssp _v cssn 78 mv 130 % acocp blanking time 16 ms acocp waiting time when acocp comparator is high and at the time the blanking time expires 0.6 s acin, acok, and acov acin rising debounce 44 ms acin falling delay 10 f s acin input bias current t a = +25 c -1 +1 f a acok detect threshold v acinok measured at acin rising, hysteresis = 40mv (typ) 1.47 1.50 1.53 v -2 +2 % acov detect threshold v acinov measured at acin rising, hysteresis = 40mv (typ) 2.05 2.10 2.15 v -2.38 +2.38 % acok sink current v acok = 0.4v, v acin = 1.7v 1 ma acok leakage current v acok = 5.5v, v acin = 1.3v, t a = +25 c 1 f a adapter present detection adapter absence detect threshold v dcin - v batt , v dcin falling 0 100 200 mv adapter detect threshold v dcin - v batt , v dcin rising 300 440 600 mv charge-pump mosfet driver pdsl gate-driver source current i pdsl-src v pdsl - v dcin = 3v, v dcin = 19v 60 f a pdsl gate-driver output voltage high v pdsl-h v dcin = 19v v dcin + 5.3 v dcin + 8 v pdsl switch control pdsl turn-off resistance r pdsl measured from pdsl to gnd 2.5 k i battery overvoltage batt overvoltage threshold v cell(ov) v batt rising, hysteresis = 20mv (typ) +100 mv/cell
integrated charger, dual main step-down controllers, and dual ldo regulators MAX17085B 8 ______________________________________________________________________________________ electrical characteristics (circuit of figure 1, no load on ldo5, ldo3, out5, out3, and ref, v cc = 5v, on3 = on5 = v cc , v dcin = v lxc = v cssp = v cssn = 19v, v bstc - v lxc = 5v, v batt = v csip = v csin = 12.6v, v vctl = v iset = 1.8v, cells = open, t a = -40c to +85c , unless otherwise noted.) (note 4) parameter symbol conditions min typ max units input supplies adapter present quiescent current i dcin + i cssp + i cssn , on3 = on5 = skip = v cc , v out3 = 3.5v, v out5 = 5.3v charging enabled 6 ma charging disabled 2.5 adapter absent quiescent current i dcin + i cssp + i cssn , on3 = on5 = skip = v cc , v out3 = 3.5v, v out5 = 5.3v v iset = 2.4v, iinp on 2.5 ma v iset = gnd 2.2 cssn input current v cssp = v cssn = 24v 2 f a batt + csip + csin + lxc input current v batt = 16.8v, adapter absent 4 f a v batt = 2v to 19v, adapter present 650 dcin input current i dcin on3 = on5 = skip = v cc , charger disabled; v out3 = 3.5v, v out5 = 5.3v 0.2 ma dcin standby supply current dcin = 5v to 24v, on3 = on5 = gnd 300 f a v cc supply current i cc on3 = on5 = skip = v cc , charger disabled; v out3 = 3.5v, v out5 = 5.3v 1.5 ma dcin input-voltage range note: ldo5 is not guaranteed to be regulation until dcin is above 6v 4.5 24 v dcin undervoltage-lockout trip point for charger v dcin(uvlo) v dcin falling 6.9 v v dcin rising 7.9 v cc undervoltagelockout threshold v cc(uvlo) falling edge of v cc , pwm disabled below this threshold 3.8 4.3 v linear regulators ldo_ output-voltage accuracy v ldo5 dcin = 6v to 24v, on5 = on3 = gnd, 0ma < i ldo5 < 100ma, on5 = gnd 4.85 5.15 v v ldo3 ldo5 = 5v, i ldo5 = 0, 0ma < i ldo3 < 50ma, on3 = gnd 3.20 3.40 ldo3 short-circuit current ldo3 = gnd 130 ma ldo5 short-circuit current ldo5 = gnd 260 ma reference ref output voltage v ref i ref = 50 f a 2.08 2.12 v main smps out5 output-voltage accuracy v out5 in = 6v to 28v, skip = ref 5.008 5.160 v out3 output-voltage accuracy v out3 in = 6v to 28v, skip = ref 3.25 3.35 v dh5 on-time t on5 in = 12v, v out5 = 5.0v (note 3) r ton = 549k i (300khz + 10%) 1073 1452 ns r ton = 202k i (800khz + 10%) 402 545
integrated charger, dual main step-down controllers, and dual ldo regulators MAX17085B _______________________________________________________________________________________ 9 electrical characteristics (continued) (circuit of figure 1, no load on ldo5, ldo3, out5, out3, and ref, v cc = 5v, on3 = on5 = v cc , v dcin = v lxc = v cssp = v cssn = 19v, v bstc - v lxc = 5v, v batt = v csip = v csin = 12.6v, v vctl = v iset = 1.8v, cells = open, t a = -40c to +85c , unless otherwise noted.) (note 4) parameter symbol conditions min typ max units dh3 on-time t on3 in = 12v, v out3 = 3.3v (note 3) r ton = 549k i (300khz - 10%) 866 1171 ns r ton = 202k i (800khz - 10%) 325 439 minimum off-time t off(min) (note 3) 330 ns extended on-time blanking duty cycle > 50%; not for production test 360 ns ultrasonic operating frequency f sw(usonic) skip = gnd 13 khz main smps fault detection out_ overvoltage trip threshold (pgood pulled low above this level) with respect to error comparator threshold 12 20 % out_ undervoltage protection trip threshold with respect to error comparator threshold 63 77 % pgood lower trip threshold with respect to error comparator threshold, falling edge, hysteresis = 15mv -350 -150 mv pgood output low voltage pgood low impedance, on5 = on3 = gnd, i sink = 4ma 0.4 v fault reset timer not for production test 7 ms main smps current limit ilim_ adjustment range 0.2 2.1 v valley current-limit threshold (adjustable) v lim _ (val) v agnd - v lx _ v ilim _ = 0.5v 40 60 mv v ilim _ = 1.00v 85 115 v ilim _ = 2.10v 174 246 main smps inputs and outputs skip threshold voltage v skip high = skip 2.3 v cc v mid = pwm 1.5 1.9 low = ultrasonic 0 0.8 skip leakage current v skip = 0 or 5v, t a = +25 c -2 +2 f a on_ input logic levels high (smps on) 2.4 v low (smps off) 0.8 smps gate drivers dh3, dh5 gate driver on- resistance r dh3 , r dh5 bst3 - lx3 and bst5 - lx5 forced to 5v; high state 3.8 i bst3 - lx3 and bst5 - lx5 forced to 5v; low state 3.8 dl3, dl5 gate-driver on- resistance r dl3 , r dl5 dl3, dl5; high state 3.5 i dl3, dl5; low state 1.5 dhc gate-driver on-resistance r dhc high state, i dhc = 10ma 3 i low state, i dhc = -10ma 2.1
integrated charger, dual main step-down controllers, and dual ldo regulators MAX17085B 10 _____________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 1, no load on ldo5, ldo3, out5, out3, and ref, v cc = 5v, on3 = on5 = v cc , v dcin = v lxc = v cssp = v cssn = 19v, v bstc - v lxc = 5v, v batt = v csip = v csin = 12.6v, v vctl = v iset = 1.8v, cells = open, t a = -40c to +85c , unless otherwise noted.) (note 4) parameter symbol conditions min typ max units dlc gate-driver on-resistance r dlc high state, i dlc = 10ma 6 i low state, i dlc = -10ma 6 charger smps dhc off-time k factor v dcin = 19v, v batt = 10v 30 40 ns/v cycle-by-cycle current-limit sense voltage v csip - v csin 120 130 mv charge-voltage regulation battery-regulation voltage accuracy v batt cells = open, vctl = ref, 2 cells -0.5 +0.5 % cells = gnd, vctl = ref, 3 cells -0.5 +0.5 cells = ldo3, vctl = ref, 4 cells -0.5 +0.5 vctl range 0 2.4 v cells 3-cell threshold 0.8 v cells 2-cell level cells = open 1.9 2.3 v cells 4-cell threshold 2.8 v charge-current regulation iset range charging current, analog setting 0.0 ref v full-charge-current accuracy (csip to csin) v csi v batt = 4v to 16.8v v iset = ref, or pwm = 100% 97 103 mv v iset = 0.6 x ref, or pwm = 60% 57.6 62.4 trickle charge-current accuracy v csi v batt = 4v to 16.8v, v iset = ref/36 or pwm = 2.7% 1.2 4.3 mv charge-current gain error -1.5 +1.5 % charge-current offset error based on v iset = ref and v iset = 0.6 x ref -1.4 +1.4 mv csip/csin/batt input voltage range 0 24 v iset power-down mode threshold v iset-sdn iset falling 20 32 mv iset rising 32 46 iset pwm threshold iset rising 2.4 v iset falling 0.8 iset frequency f iset 0.128 500 khz
integrated charger, dual main step-down controllers, and dual ldo regulators MAX17085B ______________________________________________________________________________________ 11 electrical characteristics (continued) (circuit of figure 1, no load on ldo5, ldo3, out5, out3, and ref, v cc = 5v, on3 = on5 = v cc , v dcin = v lxc = v cssp = v cssn = 19v, v bstc - v lxc = 5v, v batt = v csip = v csin = 12.6v, v vctl = v iset = 1.8v, cells = open, t a = -40c to +85c , unless otherwise noted.) (note 4) note 3: on-time and off-time specifications are measured from 50% point to 50% point at the dh pin with lx = pgnd, v bst = 5v, and a 500pf capacitor from dh to lx to simulate external mosfet gate capacitance. actual in-circuit times may be dif - ferent due to mosfet switching speeds. note 4: specifications to t a = -40c are guaranteed by design and not production tested. parameter symbol conditions min typ max units input source-current regulation input source-current limit threshold v css v cssp - v cssn 58.5 61.5 mv -2.5 +2.5 % cssp/cssn input-voltage range 5 26 v iinp current-sense amplifier voltage gain g iinp 59.9 60.1 v/v iinp output-voltage range 0 4 v iinp accuracy v cssp - v cssn = 60mv -2 +2 % v cssp - v cssn = 40mv -3 +3 v cssp - v cssn = 20mv -4 +4 iinp gain error measured at v cssp - v cssn = 60mv and v cssp - v cssn = 20mv -1.5 +1.5 % iinp offset error measured at v cssp - v cssn = 60mv and v cssp - v cssn = 20mv -0.65 +0.65 mv acin, acok , and acov acok detect threshold v acinok measured at acin rising, hysteresis = 40mv (typ) 1.47 1.53 v -2 +2 % acov detect threshold v acinov measured at acin rising, hysteresis = 40mv (typ) 2.05 2.15 v -2.38 +2.38 % acok sink current v acok = 0.4v, v acin = 1.7v 1 ma adapter present detection adapter absence detect threshold v dcin - v batt , v dcin falling 0 200 mv adapter detect threshold v dcin - v batt , v dcin rising 300 600 mv charge-pump mosfet driver pdsl gate-driver output voltage high v pdsl_h v dcin = 19v v dcin + 5.3 v
integrated charger, dual main step-down controllers, and dual ldo regulators MAX17085B 12 _____________________________________________________________________________________ typical operating characteristics (circuit of figure 1, v adp = v sys = 20v, v batt = 16.8v, ldo5 = v cc = 5v, ldo3 = 3.3v, t a = +25c, unless otherwise noted.) iinp error vs. system current (dc sweep) MAX17085B toc01 v cssp - v cssn (mv) iinp error (%) 70 60 40 50 20 30 10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 -10 0 80 v adapter = 19v adapter absent, v battery = 13v charger-current error vs. battery voltage MAX17085B toc02 battery voltage (v) charger-current error (%) 11.5 10.5 8.5 9.5 6.5 7.5 5.5 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 -0.3 4.5 12.5 i charger = 5a i charger = 4a i charger = 3a charger current vs. iset setting (analog) MAX17085B toc03 iset voltage (v) charger current (a) 1.8 1.6 1.2 1.4 0.4 0.6 0.8 1.0 0.2 1 2 3 4 5 6 7 8 9 0 0 2.0 v adapter = 19v 4a input current limit 2-cell 3-cell 4-cell charger current vs. iset setting (pwm) MAX17085B toc04 iset duty cycle (%) charger current (a) 90 80 70 60 50 40 30 20 10 1 2 3 4 5 6 7 0 0 100 v adapter = 19v 3-cell battery rs2 = 10mi 4a input current limit charger-voltage per cell vs. vctl voltage MAX17085B toc05 vctl voltage (v) charger voltage (v) 3.0 2.5 2.0 1.5 1.0 0.5 1 2 3 4 5 6 7 0 0 3.5 v adapter = 19v 3-cell battery rs2 = 10mi charger-voltage error vs. cell voltage MAX17085B toc06 cell voltage (v) charger-voltage error (%) 4.4 4.2 3.8 4.0 3.4 3.6 3.2 0.17 0.19 0.21 0.23 0.25 0.27 0.29 0.31 0.33 0.35 0.15 3.0 2-c ell 3-c ell 4-c ell charger switching frequency vs. battery voltage MAX17085B toc07 battery voltage (v) charger switching frequency (mhz) 12 9 6 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0 3 15 v adapter = 19v i charger = 3a 3-cell battery charger voltage error vs. charger current MAX17085B toc08 charger current (a) charger voltage error (%) 5 4 3 2 1 0.05 0.10 0.15 0.20 0.25 0 0 6 v adapter = 19v 4a input current limit 2-cell 3-cell 4-cell battery removal (v batt = 3v) MAX17085B toc09 pdsl 5v/div dcin 5v/div v batt 5v/div il chg 2a/div 27.5v 19v 0v 0a 100s/div 3-cell battery
integrated charger, dual main step-down controllers, and dual ldo regulators MAX17085B ______________________________________________________________________________________ 13 typical operating characteristics (continued) (circuit of figure 1, v adp = v sys = 20v, v batt = 16.8v, ldo5 = v cc = 5v, ldo3 = 3.3v, t a = +25c, unless otherwise noted.) battery removal (v batt = 11v) MAX17085B toc10 cc 1v/div v batt 5v/div dcin 5v/div il chg 2a/div 1.5v 11v 19v 0a 100s/div 3-cell battery system load transient (0a 3a 0a ) MAX17085B toc11 cc 1v/div v batt 2v/div i sysld 2a/div il chg 2a/div 1.5v 12.6v 0a 0a 400s/div 19v adapter input 3-cell battery, 3a charging current charger output short circuit MAX17085B toc12 v batt 5v/div il chg 2a/div 0v 0a 20s/div 3-cell battery power-source selector scheme when battery is present (adapter removal) MAX17085B toc13 pdsl 20v/div v batt 5v/div v sysld 10v/div v adapter 10v/div 0v 20v 12.6v 20v 10ms/div 20v adapter input, 3-cell battery power-source selector scheme when battery is present (adapter insertion) MAX17085B toc14 pdsl 20v/div v batt 5v/div v sysld 10v/div v adapter 10v/div 0v 0v 12.6v 12.6v 10ms/div 20v adapter input, 3-cell battery v ref line regulation (switching and not switching) MAX17085B toc15 input voltage (v) ref voltage (v) 24 20 16 12 8 2.092 2.094 2.096 2.098 2.100 2.090 4 28 charger and smpss are all on when switching, all off when not switching not switching switching v ref vs. ambient temperature MAX17085B toc16 ambient temperature (c) ref voltage (v) 70 60 10 20 30 40 50 2.096 2.098 2.100 2.102 2.104 2.106 2.108 2.110 2.094 0 80 charger efficiency vs. charging current MAX17085B toc17 charging current (a) efficiency (%) 7 6 1 2 3 4 5 84 86 88 90 92 94 96 98 82 0 8 v adapter = 20v 4a input current limit 2-cell 3-cell 4-cell ldo5 load regulation MAX17085B toc18 load current (ma) ldo5 voltage (v) 120 100 80 60 40 20 4.85 4.90 4.95 5.00 5.05 5.10 4.80 0 140 v adapter = 19v charger off smps5 and smps3 off ldo3 no load
integrated charger, dual main step-down controllers, and dual ldo regulators MAX17085B 14 _____________________________________________________________________________________ typical operating characteristics (continued) (circuit of figure 1, v adp = v sys = 20v, v batt = 16.8v, ldo5 = v cc = 5v, ldo3 = 3.3v, t a = +25c, unless otherwise noted.) ldo3 load regulation MAX17085B toc19 load current (ma) ldo3 voltage (v) 50 40 30 20 10 3.15 3.20 3.25 3.30 3.35 3.40 3.10 0 60 v adapter = 19v charger off smps5 and smps3 off ldo5 vs. ambient temperature MAX17085B toc20 ambient temperature (c) ldo5 voltage (v) 70 60 40 50 20 30 10 4.980 4.981 4.982 4.983 4.984 4.985 4.986 4.987 4.988 4.989 4.979 0 80 ldo3 vs. ambient temperature MAX17085B toc21 ambient temperature (c) ldo3 voltage (v) 70 60 40 50 20 30 10 3.293 3.294 3.295 3.296 3.297 3.298 3.299 3.300 3.301 3.292 0 80 ldo and ref power-up MAX17085B toc22 dcin 10v/div ldo3 2v/div ldo5 2v/div ref 1v/div 0v 0v 0v 0v 2ms/div dcin, ldo and ref power removal MAX17085B toc23 dcin 10v/div ldo3 2v/div ldo5 2v/div ref 1v/div 3.3v 19v 5v 2.1v 2ms/div ldo5 load transient (0ma 100ma 0ma) MAX17085B toc24 ldo5 (ac) 100mv/div i ldo5 100ma/div 0v 0a 4s/div on3 = on5 = gnd ldo3 load transient (0ma 50ma 0ma) MAX17085B toc25 ldo3 (ac) 100mv/div i ldo3 50ma/div 0v 0a 4s/div on3 = on5 = gnd smps5 efficiency vs. load current (charger and smps3 are off) MAX17085B toc26 load current (a) efficiency (%) 1 0.1 55 60 65 70 75 80 85 90 95 100 50 0.01 10 skip mode pwm mode 20v 12v 7v smps5 efficiency vs. load current (charger and smps3 are off) MAX17085B toc27 load current (a) efficiency (%) 1 0.1 55 60 65 70 75 80 85 90 95 100 50 0.01 10 12v input pwm mode ultrasonic mode skip mode
integrated charger, dual main step-down controllers, and dual ldo regulators MAX17085B ______________________________________________________________________________________ 15 typical operating characteristics (continued) (circuit of figure 1, v adp = v sys = 20v, v batt = 16.8v, ldo5 = v cc = 5v, ldo3 = 3.3v, t a = +25c, unless otherwise noted.) smps3 efficiency vs. load current (charger and smps5 are off) MAX17085B toc28 load current (a) efficiency (%) 1 0.1 55 60 65 70 75 80 85 90 95 100 50 0.01 10 skip mode pwm mode 20v 12v 7v smps3 efficiency vs. load current (charger and smps5 are off) MAX17085B toc29 load current (a) efficiency (%) 1 0.1 55 60 65 70 75 80 85 90 95 100 50 0.01 10 12v input pwm mode ultrasonic mode skip mode smps5 output vs. load current MAX17085B toc30 load current (a) output voltage (v) 1 0.1 5.05 5.10 5.15 5.20 5.00 0.01 10 12v input pwm mode ultrasonic mode skip mode smps3 output vs. load current MAX17085B toc31 load current (a) output voltage (v) 1 0.1 3.29 3.30 3.31 3.32 3.33 3.34 3.35 3.28 0.01 10 12v input pwm mode ultrasonic mode skip mode smps5 startup and shutdown load MAX17085B toc32 on5 5v/div out5 2v/div ldo5 200mv/div 5v 0v 0v 2ms/div smps5 startup waveforms (switching regulator) MAX17085B toc33 on5 5v/div out5 2v/div pgood 5v/div i l5 5a/div 0v 0a 0v 0v 400s/div smps5 shutdown waveforms (switching regulator) MAX17085B toc34 on5 5v/div out5 2v/div pgood 5v/div i l5 5a/div 0a 5v 5v 5v 400s/div smps5 load transient (1a 4a 1a) MAX17085B toc35 i out5 2a/div out5 100mv/div i l5 2a/div 0a 1a 5v 10s/div smps3 load transient (1a 4a 1a) MAX17085B toc36 i out3 2a/div out3 100mv/div i l3 2a/div 0a 1a 3.3v 10s/div
integrated charger, dual main step-down controllers, and dual ldo regulators MAX17085B 16 _____________________________________________________________________________________ pin description pin name function 1 lx3 inductor connection for smps3. connect lx3 to the switched side of the inductor. lx3 is the lower supply rail for the dh3 high-side gate driver. 2 bst3 boost flying capacitor connection for smps3. connect to an external capacitor as shown in figure 1. an optional resistor in series with bst3 allows the dh3 turn-on current to be adjusted. a 4.7 resistor is recommended to improve crosstalk between smpss. 3 dl3 low-side gate-driver output for smps3. dl3 swings from pgnd to ldo5. 4 out3 output voltage-sense input for smps3. out3 is an input to the quick-pwm on-time one-shot timer. out3 also serves as the feedback input for the preset 3.3v, and the discharge path when in shutdown. when out3 is in regulation, ldo3 is internally set to a lower level, and a bypass switch between out3 and ldo3 is enabled. 5 ldo3 3.3v linear regulator output. ldo3 is the output of the 3.3v linear regulator supplied from ldo5. ldo3 is switched over to out3 when smps3 is in regulation plus 200 f s. bypass ldo3 to pgnd with a 4.7 f f or greater ceramic capacitor. 6 dcin ldo5 supply input. bypass dcin with a 1 f f capacitor to pgnd. 7 ldo5 5v linear regulator output. ldo5 provides the power to the mosfet drivers. ldo5 is the output of the 5v linear regulator supplied from dcin. ldo5 is switched over to out5 when smps5 is in regulation plus 200 f s. bypass ldo5 to pgnd with a 4.7 f f or greater ceramic capacitor. 8 out5 output voltage-sense input for smps5. out5 is an input to the quick-pwm on-time one-shot timer. out5 also serves as the feedback input for the preset 5v, and the discharge path when in shutdown. when out5 is in regulation, ldo5 is internally set to a lower level, and a bypass switch between out5 and ldo5 is enabled. 9 dl5 low-side gate-driver output for smps5. dl5 swings from pgnd to ldo5 . 10 bst5 boost flying capacitor connection for smps5. connect to an external capacitor as shown in figure 1. an optional resistor in series with bst5 allows the dh5 turn-on current to be adjusted. a 4.7 resistor is recommended to improve crosstalk between smpss. 11 lx5 inductor connection for smps5. connect lx5 to the switched side of the inductor. lx5 is the lower supply rail for the dh5 high-side gate driver. 12 dh5 high-side gate-driver output for smps5. dh5 swings from lx5 to bst5. 13 dlc low-side power mosfet driver output for charger. connect to the low-side n-channel mosfet gate. 14 bstc boost flying capacitor connection for charger. connect a 0.1 f f capacitor from bstc to lxc, and a schottky diode from ldo5 to bstc. 15 lxc high-side driver source connection. connect a 0.1 f f capacitor from bstc to lxc. 16 dhc high-side power mosfet driver output for charger. connect to high-side n-channel mosfet gate. 17 pgood open-drain power-good output for smps3 and smps5. pgood is low when either smps3 or smps5 output voltage is more than 250mv (typ) below the nominal regulation threshold, during soft-start, in shutdown (on3 = on5 = gnd), and after either fault latch has been tripped. after the soft-start circuit has terminated, pgood becomes high impedance if the output is in regulation plus 200 f s. when only one smps is active, pgood monitors the active smps output. when the 2nd smps is started, pgood is blanked high-z during the 2nd smps soft-start plus 200 f s, then pgood monitors both smps outputs.
integrated charger, dual main step-down controllers, and dual ldo regulators MAX17085B ______________________________________________________________________________________ 17 pin description (continued) pin name function 18 acok ac-detect output. this open-drain output is low impedance when acin is greater than 1.5v, with a delay of 44ms. the acok output remains high impedance when the MAX17085B is powered down. connect a 100k i pullup resistor from ldo3 or ldo5 to acok . 19 csin output current-sense negative input 20 csip output current-sense positive input. connect a current-sense resistor from csip to csin. 21 batt battery voltage feedback input 22 pdsl power source switch driver output. when the adapter is not present or an overvoltage and overcurrent event is detected, the pdsl output is pulled to gnd. leave pdsl unconnected when it is not used. 23 cssn input current-sense negative input 24 cssp input current sense for positive input. connect a current-sense resistor from cssp to cssn. 25 iinp input current monitor output. iinp sources the current proportional to the current sensed across cssp and cssn. the gain from (cssp - cssn) to iinp is 60v/v: v iinp = 60 x (v cssp - v cssn ) iinp also monitors the battery-discharge current when the adapter is absent. to monitor the discharge current, set iset above the pwm threshold. pull iset to gnd to disable the iinp battery- discharge current mode. 26 cells trilevel input for setting number of cells: u cells = open; charge with 2 times the cell voltage programmed at vctl. u cells = gnd; charge with 3 times the cell voltage programmed at vctl. u cells > 2.8v; charge with 4 times the cell voltage programmed at vctl. 27 cc charger loop-compensation point. external compensation node for the charge voltage and input current-limit loops. connect a 4.7nf to 47nf capacitor to gnd. typically a 10nf capacitor works for most applications. 28 acin ac adapter detect input. acin is the input to an uncommitted comparator. the acin threshold is 1.7v for acok and 2.1v for acovp. when the acin threshold is above acok and below the acovp threshold, then pdsl is enabled. 29 vctl cell charge voltage-control input. vctl range is from gnd to ldo5. for 4.375v/cell setting, connect vctl to ref: v cell = 2.083 x v vctl 30 v cc analog supply voltage input. connect v cc to the system supply voltage with a series 47 i resistor, and bypass to analog ground using a 1 f f or greater ceramic capacitor. 31 iset dual-mode input for setting maximum charge current. in pwm mode, use input frequencies from 128hz to 500khz for charge-current setting. if there are no two edges within 20ms, iset is directly used as an analog input. in analog mode, charge current is set as follows: iset chg ref v 100mv i rs2 v = pull iset to gnd to shut down the charger. 32 ref 2.1v voltage reference and device power-supply input. bypass ref with a 1 f f capacitor to gnd. 33 gnd analog ground 34 ilim3 valley current-limit adjustment for smps3. the gnd - lx3 current-limit threshold is 1/10 the voltage present on ilim3 over a 0.2v to 2.1v range. 35 ilim5 valley current-limit adjustment for smps5. the gnd - lx5 current-limit threshold is 1/10 the voltage present on ilim5 over a 0.2v to 2.1v range.
integrated charger, dual main step-down controllers, and dual ldo regulators MAX17085B 18 _____________________________________________________________________________________ pin description (continued) standard application circuit the MAX17085B standard application circuit (figure 1) features a 4a charger, 8a outputs on smps5 and smps3, and a 100ma ldo5 and 50ma ldo3 typical of most notebook cpu applications. see table 1 for component selections. table 2 lists the component suppliers. table 1. component selection for standard applications component smps3: 3.3v, 8a, 500khz smps5: 5v, 8a, 600khz charger, 16.8v, 4a, 1.2mhz input voltage v sys = 7v to 24v v sys = 7v to 24v v adp = 18v to 20v input capacitor (2) 10 f f, 25v taiyo yuden tmk432bj106km murata grm31cr61e106k (2) 10 f f, 25v taiyo yuden tmk432bj106km murata grm31cr61e106k (2) 4.7 f f, 25v taiyo yuden tmk432bj475km murata grm31cr71e475m output capacitor c out3 (1) 100 f f, 6v, 18m i sanyo 6tpe100mi c out5 (1) 100 f f, 6v, 18m i sanyo 6tpe100mi c out(chg) (1) 4.7 f f, 25v taiyo yuden tmk432bj475km murata grm31cr71e475m inductor l3 1.5 f h, 2.1m i , 11.8a sumida cep125s-1r5 l5 1.5 f h, 2.1m i , 11.8a sumida cep125s-1r5 l chg 2 f h, 19m i , 4.5a sumida cdr7d28mn-2r0 high-side mosfet n h3 13a, 9.4m i /12m i , 30v fairchild fds6298 n h5 13a, 9.4m i /12m i , 30v fairchild fds6298 n hc 6.6a, 17m i /25m i , 30v international rectifier irf7807d1pbf low-side mosfet n l3 13a, 7.2m i /10m i , 30v fairchild fds6670a n l5 13a, 7.2m i /10m i , 30v fairchild fds6670a n lc 6.6a, 17m i /25m i , 30v international rectifier irf7807d1pbf current-limit setting 0.45v (45mv limit) r ilim3a = 66.5k i r ilim3b = 82.5k i 0.45v (45mv limit) r ilim5a = 66.5k i r ilim5b = 82.5k i pin name function 36 skip pulse-skipping control input. this tri-level input determines the operating mode for the switching regulators. high (v cc ) = pulse-skipping mode mid (1.8v) = forced-pwm operation gnd = ultrasonic mode 37 ton switching frequency setting input. an external resistor between the input power source and this pin sets the nominal switching frequency according to the following equation: f sw(nom) = 1/(c ton x (r ton + 6.5k i )) where c ton = 6pf. smps5 has a switching frequency that is 10% higher than nominal, and smps3 has a switching frequency 10% lower than nominal. r ton is high impedance when on3 = on5 = gnd. 38 on3 enable input for smps3. drive on3 high to enable smps3. drive on3 low to shut down smps3. 39 on5 enable input for smps5. drive on5 high to enable smps5. drive on5 low to shut down smps5. 40 dh3 high-side gate-driver output for smps3. dh3 swings from lx3 to bst3. ep exposed pad. internally connected to power ground (pgnd). connect the backside exposed pad to the system power ground as well.
integrated charger, dual main step-down controllers, and dual ldo regulators MAX17085B ______________________________________________________________________________________ 19 figure 1. standard application circuit v adp bstc cssp cssn dhc lxc dlc rs1 15mi csin csip cc iset iinp pwm signal r4 150ki rs2 10mi r csip * 5i r csin * 10i r batt * 10i d csip * 51.1ki n3 n4 v sys q1a dcin acin +3.3v, 8a dh3 bst3 dl3 lx3 out3 ilim3 ton skip on3 on5 off on ldo3 3.3v ldo 50ma power ground analog ground pdsl r acin2 r acin1 c dcin 1ff c ref 1ff ref c7 10nf batt ac adapter system power rail battery power rail l3 1.5fh c in(chg) 2 x 4.7ff c out(chg) 4.7ff c bstc 0.1ff c nlc 1nf c cc 10nf system current monitor n h(chg) n l(chg) l chg 2fh cells vctl gnd ref dh5 bst5 dl5 lx5 +5v, 8a out5 v sys c in5 2x 10ff 25v c out5 100ff 5v ldo 100ma c vcc 1.0ff r ilim5a r ilim5b c ldo3 4.7ff r1 47i c ldo5 4.7ff c bst5 0.1ff r bst5 4.7i l5 1.5fh acok adapter ok *components required for protection from hard shorts on batt to pgnd. **components required for proper operation. do not remove. pgood power-good r2 100ki r3 100ki ldo5 ilim5 v cc ref cells count open gnd 5v 2 3 4 battery v batt relearn 3 4 5 6 7 8 9 10 40 39 38 37 36 35 34 33 32 31 26 21 22 23 24 25 11 12 13 14 15 16 17 18 19 20 30 29 28 27 2 1 5v ldo n4 provides reverse adapter protection. replace with diode if reverse adapter protection is not needed. q1b c in3 2 x 10ff 25v c out3 100ff c bst3 0.1ff r bst3 4.7i n5 pad MAX17085B n h5 n l5 c iinp 0.1ff r ton 300ki n h3 v sys n l3 r ilim3a r ilim3b d 3 ** d 5 **
integrated charger, dual main step-down controllers, and dual ldo regulators MAX17085B 20 _____________________________________________________________________________________ detailed description the MAX17085B integrated charger and main step- down controllers are ideal for notebook applications where board space and solution cost are key require - ments. together with the integrated, always-on 100ma ldo5 and 50ma ldo3, the MAX17085B provides a complete power solution for the notebook in the off-state, standby-state, and full active state. a functional diagram of the MAX17085B is shown in figure 2. charger the MAX17085B uses a new thermally optimized high- frequency architecture that reduces the output capaci - tance and inductance, resulting in smaller pcb area and lower cost. the MAX17085B charger includes all the necessary functions to charge li+, nimh, and nicd batteries. an all n-channel synchronous-rectified step- down dc-dc converter is used to implement a precision constant-current, constant-voltage charger. the charge current and input current-limit sense amplifiers have low- input offset errors (200 f v typ), allowing the use of small- valued sense resistors. main smps the 5v and 3.3v main smpss in the MAX17085B use maxims quick-pwm pulse-width modulator, specifically designed for handling fast load steps while maintaining a relatively constant operating frequency and inductor operating point over a wide range of input voltages. the quick-pwm architecture circumvents the poor load-tran - sient timing problems of fixed-frequency current-mode pwms while also avoiding the problems caused by widely varying switching frequencies in conventional constant- on-time and constant-off-time pwm schemes. 100ma 5v linear regulator (ldo5) and bias supply (v cc ) the MAX17085B includes a high-current (100ma), always-on fixed 5v linear regulator (ldo5). ldo5 is required to generate the 5v bias supply necessary to power up the switching regulators, and as the input supply to the 3.3v linear regulator (ldo3). once the 5v switching regulator (smps5) is enabled and in regula - tion, ldo5 is bypassed by an internal switch from out5 to ldo5. after switchover, the ldo5 pin can source 200ma. ldo5 starts up as soon as dcin has valid volt - age (around 2.5v), and regulates to ~ 4.5v using an internal crude reference. ref starts at the same time, and once ref is in regulation, ldo5 switches over to use the accurate ref, and regulates up to 5v. the MAX17085B requires a low-noise 5v bias supply (v cc ) for its internal circuitry. typically, this 5v bias is supplied by ldo5 through a lowpass filter. the total sup - ply current required for the MAX17085B is: i bias(max) = i cc(max) + f sw5 q g5 + f sw3 q g3 + f swc q gc 45ma to 90ma (typ) 50ma, 3.3v linear regulator (ldo3) a lower current (50ma), always-on fixed 3.3v linear regu - lator, is also included in the MAX17085B. once the 3.3v switching regulator (smps3) is enabled and in regula - tion, ldo3 is bypassed by an internal switch from out3 to ldo3. after switchover, the ldo3 pin can source more than 200ma. ldo3 starts up as soon as ref is in regulation. this limits the inrush current by sequencing ldo5 to start before ldo3. table 2. component suppliers supplier website avx corp. www.avxcorp.com central semiconductor corp. www.centralsemi.com fairchild semiconductor www.fairchildsemi.com international rectifier www.irf.com kemet corp. www.kemet.com nec/tokin america www.nec-tokinamerica.com panasonic corp. www.panasonic.com/industrial philips/nxp semiconductor www.semiconductors.philips.com pulse engineering www.pulseeng.com supplier website renesas technology corp. www.renesas.com sanyo electric co., ltd. www.sanyodevice.com sumida corp. www.sumida.com taiyo yuden www.t-yuden.com tdk corp. www.component.tdk.com toko america, inc. www.tokoam.com vishay (dale, siliconix) www.vishay.com wrth elektronik gmbh & co. kg www.we-online.com
integrated charger, dual main step-down controllers, and dual ldo regulators MAX17085B ______________________________________________________________________________________ 21 thermal-fault protection (t shdn ) the MAX17085B features a thermal fault-protection cir - cuit. when the junction temperature rises above +160 n c, a thermal sensor activates the fault latch, pulls pgood low, enables the 20 i discharge circuit, and disables the controllerdh and dl pulled low. after the junction temperature cools by 50 n c, the controller automatically restarts. this protects the internal ldo when a sustained overcurrent or output short circuit occurs. por, uvlo when v cc rises above the power-on reset (por) thresh - old, the MAX17085B clears the fault latches and resets the soft-start circuit, preparing the controller for power- up. however, the v cc undervoltage-lockout (uvlo) circuitry inhibits switching until v cc reaches its 4.2v (typ) uvlo threshold. when v cc drops below the uvlo threshold (falling edge), the controller stops switching, pulling dh and dl low. when the 1.5v por falling edge threshold is reached, the dl state no longer matters since there is not enough voltage to force the switching mosfets into a low on-resistance state, so the controller pulls dl high, allowing a soft discharge of the output capaci - tors (damped response). however, if the v cc recovers before reaching the falling por threshold, dl remains low until the error comparator has been properly pow - ered up and triggers an on-time. when dcin is high enough for ldo5 to be in regulation and v cc to be above its uvlo, the main smps can begin running. charger operation requires dcin to be above its 7.7v uvlo threshold. figure 2. functional diagram ilim5 ilim3 dh3 bst3 dl3 lx3 cssp cssn out5 ton on5 skip smps3 driver block out3 on3 ref skip out5 fb dh5 bst5 dl5 lx5 driver skip pgood pgood logic out5 out3 ton block ton adjust ldo5 dcin ldo5 ldo5 ldo3 ldo3 dhc bstc dlc lxc driver lvc block batt iset csip csin vctl pdsl charge pump dcin current- sense amp iinp toff block acok acin ac comp acov ref v cc gnd ref vbatt cells cc pad acov current- sense amp ldo5 MAX17085B
integrated charger, dual main step-down controllers, and dual ldo regulators MAX17085B 22 _____________________________________________________________________________________ charger detailed description the MAX17085B charger has three regulations loops: a voltage-regulation loop (ccv) and two current-regulation loops (cci and ccs). the loops operate independently of each other. the ccv voltage-regulation loop monitors batt to ensure that its voltage never exceeds the volt - age set by vctl and cells. the cci battery charge current-regulation loop monitors current delivered to batt to ensure that it never exceeds the current limit set by iset. the charge current-regulation loop is in control as long as the battery voltage is below the set point. when the battery voltage reaches its set point, the voltage-regulation loop takes control and maintains the battery voltage at the set point. a third loop (ccs) takes control and reduces the charge current when the adapter current exceeds the input current limit. the cci current loop is internally compensated while the ccs and ccv loops are externally compensated with a capacitor at the cc pin. the new thermally optimized high-frequency architecture controls the power dissipation in the high-side mosfet, resulting in reduced output capacitance and inductance. setting the charge voltage the MAX17085B features separate control inputs to set the per-cell voltage and the number of cells in series. the vctl input sets the per-cell voltage, while the cells input sets the total number of cells in series. together, these two inputs set the charge voltage at the batt input, providing a flexible way to support different cell types and different battery-pack configurations. setting the per-cell charge voltage (vctl) the MAX17085B supports charge voltages of 4.0v/cell to 4.4v/cell based on the following equation: batt v cell 2.083 vctl = the dynamic range of the vctl input is limited, so it is possible to achieve 0.5% charge voltage accuracy using resistive voltage-dividers composed of 1% accu - rate resistors. figure 3 shows a simple method to set two different cell voltages using a logic output from the embedded controller. connecting vctl to ref = 2.10v, which gives 4.375v/cell. setting the number of cells (cells) the trilevel cells input allows simple switching between 2, 3, and 4 cells in series. setting charge current (iset) the iset input controls the voltage across current-sense resistor rs2. iset can accept either analog or digital inputs. the full-scale differential voltage between csip and csin is 100mv (5a for rs2 = 20m i ). important: keep iset low during the initial power-up of the MAX17085B. wait 10ms to allow pdsl to reach its final voltage before enabling the battery charger. analog iset when the MAX17085B powers up and the charger is ready, if there are no two clock edges within 20ms, the circuit assumes iset is an analog input, and disables the pwm filter block. for iset analog input, set iset accord - ing to the following equation: iset chg ref v 100mv i rs2 v = the input range for iset is from 0 to ref. to shut down the charger, pull iset below 26mv. figure 3. vctl setting table 3. cells pin setting vctl control r1 r2 r3 vctl ref v ref o r2 r1 + r2 v cell (h) = 2.083 o v ref o r2//r3 r1 + r2//r3 v cell (l) = 2.083 o MAX17085B cells pin voltage cells count setting open 2 charge with 2 times the cell voltage programmed at vctl gnd 3 charge with 3 times the cell voltage programmed at vctl > 2.8v 4 charge with 4 times the cell voltage programmed at vctl
integrated charger, dual main step-down controllers, and dual ldo regulators MAX17085B ______________________________________________________________________________________ 23 digital iset if there are two clock edges on iset within 20ms, the pwm filter is enabled and iset accepts digital pwm input. the pwm filter accepts the digital signal with a frequency from 128hz to 500khz. zero duty cycle shuts down the MAX17085B, and the 99% duty cycle cor - responds to full scale (100mv) across csip and csin. the pwm filter has a dac with 8-bit resolution that corre - sponds to equivalent v csip - v csin steps. each step is: ref step v v 0.391mv (7.8ma with rs2 20m ) 256 21 = = = ? ? choose a current-sense resistor (rs2) to have a suf - ficient power dissipation rating to handle the full-charge current. the current-sense voltage may be reduced to minimize the power dissipation period. however, this may degrade accuracy due to the current-sense ampli - fiers input offset (200v). see the typical operating characteristics to estimate the charge-current accuracy at various set points. input source current setting input current limit the total input current, from a wall adapter or other dc source, is the sum of the system supply current and the current required by the charger. when the input current exceeds the set input current limit, the control - ler decreases the charge current to provide priority to system load current. system current normally fluctuates as portions of the system are powered up or down. the input-current-limit circuit reduces the power requirement of the ac wall adapter, which reduces adapter cost. as the system supply rises, the available charge current drops linearly to zero. thereafter, the total input current can increase without limit. the total input current can be estimated as follows: chg batt input load adp i v i i v = + where e is the efficiency of the dc-to-dc converter (typi - cally 85% to 95%). in the MAX17085B, the voltage across cssp and cssn is constant at 60mv. choose the current-sense resistor, rs1, to set the input current limit. for example, for 4a input current limit choose rs1 = 15m i . for the input current-limit settings, which cannot be achievable with standard sense resistor values, use a resistive voltage- divider between cssp and cssn to tune the setting. ac adapter overcurrent (acoc) when the input current is 1.3 times the input current-limit setting, pdsl is pulled to gnd after a 16ms blanking time. this turns off the adapter switch and enables the battery selector switch. after 0.6s, pdsl is reenabled. if the fault condition persists, the cycle is repeated, until the third time when the charger is latched off. to clear the fault latch, remove the adapter and allow dcin to fall below its uvlo threshold before reinserting the adapter. analog input current-monitor output iinp monitors the system-input current, which is sensed across cssp and cssn. the voltage at iinp is propor - tional to the input current: ( ) iinp iinp adp iinp cssp cssn v g i rs1 v 60 v - v = = where i adp is the dc current supplied by the ac adapt - er, g iinp is the transconductance of the sense amplifier (60v/v typ), and rs1 is the resistor connected between cssp and cssn. when the adapter is absent, drive iset above 2.1v to enable iinp during battery discharge. ac adapter detection (acin, acok , acov) the acin input goes to two internal comparators, one for adapter detection ( acok ) and another for adapter overvoltage detection (acov). when acin is above 1.5v, the open-drain acok output becomes low imped - ance after 44ms. when acin rises above 2.1v, the MAX17085B detects an acov condition and immediately pulls pdsl to gnd, turning off the adapter selection switch and enabling the battery selector switch. this protects the system rail from excessively high voltages that might violate the absolute maximum ratings of the downstream components. note that acok remains low even when acin is above the acov threshold. use a resistive voltage-divider from the adapters output to the acin pin to set the appropriate detection thresh - old. connect a 100k i pullup resistor between ldo3 or ldo5 and acok . automatic power-source selection (pdsl) the MAX17085B integrates a charge pump to drive the gate of n-channel adapter selector switches (n3 and q1a) and the p-channel battery-selector switch (q1b). when the adapter is present, pdsl is driven 8v above v dcin so that n3 and q1a are on, and q1b is off. see the operating conditions section for the definition of adapter present.
integrated charger, dual main step-down controllers, and dual ldo regulators MAX17085B 24 _____________________________________________________________________________________ when the adapter voltage is removed and the adapter is absent, the charger is disabled and pdsl is pulled to gnd. n3 and q1a turn off, and q1b turns on to supply power to the system from the battery. operating conditions table 4 defines the MAX17085B charger operating conditions. charger smps the MAX17085B employs a synchronous step-down dc-dc converter with an n-channel high-side mosfet switch and an n-channel low-side synchronous rectifier. the charger features a controlled inductor current ripple architecture, current-mode control scheme with cycle- by-cycle current limit. the controllers off-time (t off ) is adjusted to keep the high-side mosfet junction tem - perature constant. in this way, the controller switches faster when the high-side mosfet has available thermal capacity. this allows the inductor current ripple and the output voltage ripple to decrease so that smaller and cheaper components can be used. the controller can also operate in discontinuous conduction mode for improved light-load efficiency. the operation of the dc-to-dc controller is determined by the following five comparators as shown in the func - tional diagram in figures 2 and 4: u the imin comparator triggers a pulse in discontinu - ous mode when the accumulated error is too high. imin compares the control signal (lvc) against 5mv (typ) (referred at v csip - v csin) . when lvc is less than 5mv, dhc and dlc are both forced low. indirectly, imin sets the peak inductor current in dis - continuous mode. u the ccmp comparator is used for current-mode regulation in continuous conduction mode. ccmp compares lvc against the inductor current. the high- side mosfet on-time is terminated when the csi voltage is higher than lvc. u the imax comparator provides a secondary cycle- by-cycle current limit. imax compares csi to the current limit programmed at iset. the high-side mosfet on-time is terminated when the current- sense signal exceeds the programmed limit. a new table 4. charger operating mode truth table note 5: adapter is present when v dcin - v csin > 420mv with v dcin rising, and absent when v dcin - v csin < 120mv with v dcin falling. dcin adapter present (note 5) input current v cssp - v cssn acin iset pdsl charger state iinp comments x no x x < 1v gnd off off x no x x > 1v gnd off on < uvlo yes > ocp threshold x x gnd off on < uvlo yes x v acin > v acinov x gnd off on < uvlo yes < ocp threshold v acinok < v acin and v acin < v acinov x v dcin + 8v off on > uvlo yes x v acinok < v acin and v acin < v acinov x gnd off on adapter overvoltage fault > uvlo yes > ocp threshold x x gnd off on adapter overcurrent fault > uvlo yes < ocp threshold v acinok < v acin and v acin < v acinov < iset shutdown threshold v dcin + 8v off on iset shutdown > uvlo yes < ocp threshold < acov threshold > iset shutdown threshold v dcin + 8v on (iset control) on
integrated charger, dual main step-down controllers, and dual ldo regulators MAX17085B ______________________________________________________________________________________ 25 cycle cannot start until the imax comparators output goes low. u the zcmp comparator provides zero-crossing detec - tion during discontinuous conduction. zcmp com - pares the current-sense feedback signal to 10mv. when the current-sense signal is lower than the 10mv threshold, the comparator output is high and dlc is turned off. u the ov comparator is used to prevent overvoltage at the output due to battery removal. ov compares batt against the vctl and cells settings. when batt is 40mv/cell above the set value, the ov com - parator output goes high and the high-side mosfet on-time is terminated. dhc and dlc remain off until the ov condition is removed. ccv, cci, ccs, and lvc control blocks the MAX17085B controls input current (ccs control loop), charge current (cci control loop), or charge voltage (ccv control loop), depending on the operat - ing condition. the three control loopsccv, cci, and ccsare brought together internally at the lowest voltage clamp (lvc) amplifier. the output of the lvc amplifier is the feedback control signal for the dc-dc controller. the minimum voltage at the ccv, cci, or ccs appears at the output of the lvc amplifier and clamps the other control loops to within 0.3v above the control point. clamping the other two control loops close to the lowest control loop ensures fast transition with minimal overshoot when switching between different control loops (see the compensation section). the cci loop is compensated internally, while the ccs and ccv loops are compensated externally using a shared capacitor on the cc pin. figure 4. charger functional diagram ccmp r imin q imax q s off-time one-shot v csi limit 5mv csi lvc dhc driver dlc driver off-time compute cssp bdiv vctl + 40mv csin zcmp 10mv ovp
integrated charger, dual main step-down controllers, and dual ldo regulators MAX17085B 26 _____________________________________________________________________________________ continuous conduction mode with sufficiently large charge current, the MAX17085B's inductor current never crosses zero, which is defined as continuous conduction mode. the controller starts a new cycle by turning on the high-side mosfet and turn - ing off the low-side mosfet. when the charge-current feedback signal (csi) is greater than the control point (lvc), the ccmp comparator output goes high and the controller initiates the off-time by turning off the high- side mosfet and turning on the low-side mosfet. the operating frequency is governed by the off-time and is dependent upon v csin and v dcin . the on-time can be determined using the following equation: ripple on dcin batt l i t v - v = where: batt off ripple v t i l = the switching frequency can then be calculated: sw on off 1 f t t = + at the end of the computed off-time, the controller initi - ates a new cycle if the control point (lvc) is greater than 5mv (referred at v csip - v csin ), and the peak charge current is less than the cycle-by-cycle current limit. restated another way, imin must be high, imax must be low, and ovp must be low for the controller to initiate a new cycle. if the peak inductor current exceeds imax comparator threshold or the output voltage exceeds the ovp threshold, then the on-time is terminated. the cycle-by-cycle current limit effectively protects against overcurrent and short-circuit faults. if during the off-time the inductor current goes to zero, the zcmp comparator output pulls high, turning off the low-side mosfet. both the high- and low-side mosfets are turned off until another cycle is ready to begin. zcmp causes the MAX17085B to enter into the discontinuous conduction mode (see the discontinuous conduction section). discontinuous conduction the MAX17085B can also operate in discontinuous conduction mode to ensure that the inductor current is always positive. the MAX17085B enters discontinuous conduction mode when the output of the lvc control point falls below 5mv (referred at v csip - v csin ). for rs2 = 20m i , this corresponds to peak inductor current to be 250ma. in discontinuous mode, a new cycle is not started until the lvc voltage rises above 5mv. discontinuous mode operation can occur during a conditioning charge of overdischarged battery packs, when the charge current has been reduced sufficiently by the ccs control loop, or when the charger is in constant-voltage mode with a nearly full battery pack. compensation the charge voltage, charge current, and input current- limit regulation loops are compensated separately and independently. the charge-current limit loop, cci, is compensated internally, while the input current limit and charge-voltage loops, ccs and ccv, are compensated externally using a shared capacitor at the cc pin. for most applications, it is sufficient to place a 10nf capaci - tor from cc to gnd. main smps detailed description the main smps of the MAX17085B consists of two inde - pendent switching regulators that generate a 3.3v and a 5v output. the regulators use the quick-pwm control architec - ture for simplicity, low pin count, and fast transient response. an extended on-time feature further improves output voltage sag for high-duty-cycle applications. free-running constant-on-time pwm controller with input feed-forward the quick-pwm control architecture is a pseudo-fixed- frequency, constant on-time, current-mode regulator with voltage feed-forward. this architecture relies on the output filter capacitors esr to act as a current-sense resistor, so the feedback ripple voltage provides the pwm ramp signal. the control algorithm is simple: the high-side switch on-time is determined solely by a one-shot whose pulse width is inversely proportional to input voltage and directly propor - tional to output voltage. another one-shot sets a minimum off-time (270ns typ). the on-time one-shot is triggered if the error comparator is low, the low-side switch current is below the valley current-limit threshold, and the minimum off-time one-shot has timed out. on-time one-shot the heart of the pwm core is the one-shot that sets the high-side switch on-time. this fast, low-jitter, adjustable one-shot includes circuitry that varies the on-time in response to battery and output voltage. the high-side switch on-time is inversely proportional to the battery voltage as sensed by the ton input, and proportional to the output voltage:
integrated charger, dual main step-down controllers, and dual ldo regulators MAX17085B ______________________________________________________________________________________ 27 t on5 = v out5 /v system x t sw(nom) /1.1 t on3 = v out3 /v system x t sw(nom) /0.9 t sw(nom) = c ton x r ton + 6.5k i where c ton = 6pf. high-frequency (~ 600khz nominal) operation optimizes the application for the smallest component size. efficiency trade-off due to higher switching losses is not so signifi - cant for higher output voltage rails like 5v and 3.3v. for continuous conduction operation, the actual switch - ing frequency can be estimated by: out dis sw on sys chg v v f t (v v ) + = + where v dis is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rec - tifier, inductor, and pcb resistances; v chg is the sum of the resistances in the charging path, including the high- side switch, inductor, and pcb resistances; and t on is the on-time calculated by the MAX17085B. extended on-time during heavy load transients, the main smps can issue an extended on-time to increase the inductor current ramp and reduce output voltage sag, thereby reducing output capacitance requirement. the extended on-time feature is ideal for high-duty-cycle conditions where the voltage across the inductor (v sys - v out ) is less than the output voltage. the extended on-time is twice as long as the normal on-time. a minimum off-time follows after each extended on-time. the extended on-time is allowed when the following con - ditions are met: u inductor valley current at the start of the first on pulse is less than 50% of the current-limit setting. u greater than 50% duty cycle. modes of operation forced-pwm mode (skip = 1.8v) the low-noise forced-pwm mode (skip = 1.8v) dis - ables the zero-crossing comparator, which controls the low-side switch on-time. this forces the low-side gate- drive waveform to constantly be the complement of the high-side gate-drive waveform, so the inductor current reverses at light loads while dh maintains a duty factor of v out / v sys . the benefit of forced-pwm mode is to keep the switching frequency fairly constant. however, forced-pwm operation comes at a cost: the no-load 5v bias current remains between 15ma to 35ma per phase at 600khz, depending on the mosfet selection. automatic pulse-skipping mode (skip = 3.3v or 5v) in skip mode (skip = 3.3v or 5v), an inherent automatic switchover to pfm takes place at light loads. this swi - tchover is affected by a comparator that truncates the low-side switch on-time at the inductor currents zero crossing sensed across lx and agnd. in discontinuous conduction (skip = 3.3v or 5v, and i out < i load(skip) ), the output voltage has a dc regulation level higher than the error comparator threshold. ultrasonic mode (skip = gnd) forcing skip low (skip = gnd) activates a unique pulse-skipping mode with a minimum switching frequen - cy of 20khz. this ultrasonic pulse-skipping mode elimi - nates audio-frequency modulation that would otherwise be present when a lightly loaded controller automatically skips pulses. in ultrasonic mode, the controller automati - cally transitions to fixed-frequency pwm operation when the load reaches the same critical conduction point (i load(skip) ) that occurs when normally pulse skipping. an ultrasonic pulse occurs (figure 5) when the control - ler detects that no switching has occurred within the last 45 f s. once triggered, the ultrasonic circuitry pulls dl high, turning on the low-side mosfet. this induces a negative inductor current. a negative current limit of 72mv protects against excessive negative currents when dl is turned on. after the output drops below the regulation voltage, the controller turns off the low-side mosfet (dl pulled low) and triggers a constant on-time (dh driven high). when the on-time has expired, the controller reenables the low- side mosfet until the inductor current drops below the zero-crossing threshold. starting with a dl pulse greatly reduces the peak output voltage when compared to starting with a dh pulse. figure 5. ultrasonic waveforms on-time (t on ) 0 zero-crossing detection 45fs (typ) inductor current
integrated charger, dual main step-down controllers, and dual ldo regulators MAX17085B 28 _____________________________________________________________________________________ valley current-limit protection the current-limit circuit employs a unique valley cur - rent-sensing algorithm that senses the inductor current through the low-side mosfet, across lx to agnd. if the current through the low-side mosfet exceeds the valley current-limit threshold, the pwm controller is not allowed to initiate a new cycle. the actual peak current is greater than the valley current-limit threshold by an amount equal to the inductor ripple current. therefore, the exact current-limit characteristic and maximum load capability are a function of the inductor value and battery voltage. when combined with the uvp, this current-limit method is effective in almost every circumstance. soft-start and soft-shutdown the MAX17085B includes voltage soft-start and passive soft-shutdown. during startup, the slew rate control softly slews the internal target voltage over a 2ms startup peri - od. this long startup period reduces the inrush current during startup. startup is always in skip mode regardless of the skip pin setting. when on3 or on5 is pulled low, or the output undervolt - age fault latch is set, the regulator immediately forces dl and dh low, and enables the internal 20 i discharge fet from the out pin to gnd. output voltage when the inductor continuously conducts, the MAX17085B regulates the valley of the output ripple, so the actual dc output voltage is lower than the slope com - pensated trip level by 50% of the output ripple voltage. for pwm operation (continuous conduction), the output voltage is accurately defined by the following equation: ripple out nom v v v 2 = + where v nom is the nominal feedback voltage and v ripple is the output ripple voltage (v ripple = esr x d i inductor as described in the output capacitor selection section). in discontinuous conduction (i out < i load(skip) ), the longer off-times allow the slope compensation to increase the threshold voltage by as much as 1%, so the output voltage regulates slightly higher than it would in pwm operation. power-good output (pgood) pgood is the open-drain output that continuously moni - tors the output voltage for undervoltage and overvoltage conditions. pgood is actively held low when either output voltage is more than 250mv (typ) below the nomi - nal regulation threshold, during soft-start, in shutdown (on3 = on5 = gnd), and after either fault latch has been tripped. after the soft-start circuit has terminated, pgood becomes high impedance if the output is in regulation plus 200 f s. when only one smps is active, pgood monitors the active smps output. when the 2nd smps is started, pgood is blanked high-z during the 2nd smps soft-start plus 200 f s, then pgood monitors both smps outputs. for a logic-level pgood output voltage, connect an external pullup resistor between pgood and ldo3. a 100k i pullup resistor works well in most applications. fault protection the main smps features overvoltage and undervoltage fault protection that shuts down the smps. to prevent false trips from latching off the main smps, the fault latch is automatically reset after approximately 7ms. if the on pins are still high, the respective smps restarts. if the fault is still present, the shutdown and restart cycle repeats. after the 4th time, the latch is permanently set and requires toggling on3 or on5, or pulling v cc below uvlo to start again. the charger operation is not affected by the smps faults. overvoltage protection (ovp) when the output voltage rises 16% above the fixed regu - lation voltage, the controller immediately pulls pgood low, sets the overvoltage fault latch, and immediately pulls the respective dl high, clamping the output fault to gnd. the nonfaulted side also enters the shutdown state. undervoltage protection (uvp) when the output voltage drops 30% below the fixed regulation voltage and the inductor current exceeds the current limit, the controller immediately pulls pgood low, sets the undervoltage fault latch, and discharges both smps outputs.
integrated charger, dual main step-down controllers, and dual ldo regulators MAX17085B ______________________________________________________________________________________ 29 charger design procedure inductor selection the selection criteria for the inductor trades off efficien - cy, transient response, size, and cost. the MAX17085B's charger combines all the inductor trade-offs in an opti - mum way using the high-frequency current-mode archi - tecture. high-frequency operation permits the use of a smaller and cheaper inductor, and consequently results in smaller output ripple and better transient response. the charge current, ripple, and operating frequency (off-time) determine the inductor characteristics. for optimum efficiency, choose the inductance according to the following equation: 2 adp chg max chg kv l 4 lir i = where k = 35ns/v. for optimum size and inductor current ripple, choose lir max = 0.4, which sets the ripple current to 40% of the charge current and results in a good balance between inductor size and efficiency. higher inductor values decrease the ripple current. smaller inductor values save cost but require higher saturation current capabili - ties and degrade efficiency. inductor l chg must have a saturation current rating of at least the maximum charge current plus 1/2 of the ripple current ( d il): chg sat chg il i i 2 ? = + the ripple current is determined by: 2 adp chg chg kv il 4 l ? = ? output capacitor selection the output capacitor absorbs the inductor ripple cur - rent and must tolerate the surge current delivered from the battery when it is initially plugged into the charger. as such, both capacitance and esr are important parameters in specifying the output capacitor as a filter. beyond the stability requirements, it is often sufficient to make sure that the output capacitors esr is much lower than the batterys esr. either tantalum or ceramic capacitors can be used on the output. ceramic devices are preferable because of their good voltage ratings and resilience to surge currents. choose the output capacitor based on: table 5. main smps fault protection and shutdown operation mode controller state driver state shutdown (on_ = high to low) internal error amplifier target immediately resets to gnd. dl and dh immediately pulled low; 20 i output discharge active. output uvp (latched with 4 autorestarts) internal error amplifier target immediately resets to gnd. after ~ 7ms timeout, the controller restarts if on_ is still high. dl and dh immediately pulled low; 20 i output discharge active. output ovp (latched with 4 autorestarts) controller shuts down and the internal error amplifier target resets to gnd. after ~ 7ms timeout, the controller restarts if on_ is still high. dl immediately driven high; dh pulled low; 20 i output discharge active. thermal fault (latched with 4 autorestarts) smps controller disabled (assuming on_ pulled high). internal error amplifier target immediately resets to gnd. after the die temperature falls by ~ 50 n c, the controller restarts if on_ is still high. dl and dh pulled low; 20 i output discharge active. v cc uvlo falling edge smps controller disabled (assuming on_ pulled high), internal error amplifier target immediately resets to gnd. dl and dh pulled low; 20 i output discharge active. v cc uvlo rising edge smps controller enabled (assuming on_ pulled high), controller ramps up the output to the preset voltage. dl and dh held low and 20 i output discharge active until v cc passes the uvlo threshold. v cc por smps inactive. dl and dh pulled low; 20 i output discharge active.
integrated charger, dual main step-down controllers, and dual ldo regulators MAX17085B 30 _____________________________________________________________________________________ ripple out(chg) cap-bias sw batt i c k f 8 v = d where k cap-bias is the derating factor for the capacitor due to dc voltage bias; k cap-bias is typically 2 for 25v rated capacitors. for f sw = 1.2mhz, i ripple = 1a, d v batt = 70mv, 4.7 f f is the closest common capacitor for c out(chg) . if the internal resistance of the battery is close to the esr of the output capacitor, the voltage ripple is shared with the battery, and is less than calculated. main smps design procedure firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). the pri - mary design trade-off lies in choosing a good switching frequency and inductor operating point, and the follow - ing four factors dictate the rest of the design: u input voltage range: the maximum value (v sys(max) ) must accommodate the worst-case, high ac-adapter voltage. the minimum value (v sys(min) ) must account for the lowest battery voltage after drops due to con - nectors, fuses, and battery selector switches. if there is a choice at all, lower input voltages result in better efficiency. u maximum load current: there are two values to consider. the peak load current (i load(max) ) deter - mines the instantaneous component stresses and fil - tering requirements and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. the continuous load cur - rent (i load ) determines the thermal stresses and thus drives the selection of input capacitors, mosfets, and other critical heat-contributing components. u switching frequency: this choice determines the basic trade-off between size and efficiency. the opti - mal frequency is largely a function of maximum input voltage due to mosfet switching losses that are proportional to frequency and v in 2 . the optimum fre - quency is also a moving target, due to rapid improve - ments in mosfet technology that are making higher frequencies more practical. u inductor operating point: this choice provides trade-offs between size vs. efficiency and transient response vs. output ripple. low inductor values pro - vide better transient response and smaller physical size, but also result in lower efficiency and higher output ripple due to increased ripple currents. the minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduc - tion (where the inductor current just touches zero with every cycle at maximum load). inductor values lower than this grant no further size-reduction benefit. the optimum operating point is usually found between 20% and 50% ripple current. for high-duty-cycle applications, select an lir value of ~ 0.4. when pulse skipping (skip high and light loads), the inductor value also determines the load-current value at which pfm/pwm switchover occurs. inductor selection the switching frequency and inductor operating point determine the inductor value as follows: ( ) out sys out sys sw load(max) v v - v l v f i lir = for example: i load(max) = 8a, v sys = 12v, v out = 5v, f sw = 600khz, 40% ripple current or lir = 0.4: ( ) 5v 12v - 5v l 1.5 h 12v 600khz 8a 0.4 = = f find a low-loss inductor having the lowest possible dc resistance that fits in the allotted dimensions. ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200khz. the core must be large enough not to saturate at the peak induc - tor current (i peak ): peak load(max) lir i i 1 2 ? ? = + ? ? ? ? most inductor manufacturers provide inductors in stan - dard values, such as 1.0 f h, 1.5 f h, 2.2 f h, 3.3 f h, etc. also look for nonstandard values, which can provide a better compromise in lir across the input voltage range. if using a swinging inductor (where the no-load inductance decreases linearly with increasing current), evaluate the lir with properly scaled inductance values. output capacitor selection output capacitor selection is determined by the control - ler stability requirements, and the transient soar and sag requirements of the application.
integrated charger, dual main step-down controllers, and dual ldo regulators MAX17085B ______________________________________________________________________________________ 31 output capacitor esr the output filter capacitor must have low enough equivalent series resistance (esr) to meet output ripple and load- transient requirements, yet have high enough esr to satisfy stability requirements. for processor core voltage converters and other applica - tions where the output is subject to violent load transients, the output capacitors size depends on how much esr is needed to prevent the output from dipping too low under a load transient. ignoring the sag due to finite capacitance: step esr load(max) v r i d in applications without large and fast load transients, the output capacitors size often depends on how much esr is needed to maintain an acceptable level of output voltage ripple. the output voltage ripple of a step-down controller equals the total inductor ripple current multiplied by the out - put capacitors esr. therefore, the maximum esr required to meet ripple specifications is: ripple esr load(max) v r i lir the actual capacitance value required relates to the physi - cal size needed to achieve low esr, as well as to the chemistry of the capacitor technology. thus, the capacitor is usually selected by esr and voltage rating rather than by capacitance value (this is true of tantalums, os-cons, polymers, and other electrolytics). when using low-capacity filter capacitors, such as ceramic capacitors, size is usually determined by the capacity need - ed to prevent v sag and v soar from causing problems during load transients. generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the transient response section). however, low-capacity filter capacitors typically have high esr zeros that may affect the overall stability (see the output capacitor stability considerations section). output capacitor stability considerations for quick-pwm controllers, stability is determined by the value of the esr zero relative to the switching frequency. the boundary of instability is given by the following equation: sw esr f f g where: esr esr out 1 f 2 r c = g for a typical 600khz application, the esr zero frequency must be well below 200khz, preferably below 100khz. tantalum and os-con capacitors in widespread use at the time of publication have typical esr zero frequen - cies of 25khz. in the design example used for inductor selection, the esr needed to support 25mv p-p ripple is 25mv/1.2a = 20.8m i . one 220 f f/4v sanyo polymer (tpe) capacitor provides 15m i (max) esr. this results in a zero at 48khz, well within the bounds of stability. do not put high-value ceramic capacitors directly across the feedback sense point without taking precautions to ensure stability. large ceramic capacitors can have a high esr zero frequency and cause erratic, unstable operation. unstable operation manifests itself in two related but distinctly different ways: double-pulsing and fast-feedback loop instability. double-pulsing occurs due to noise on the output or because the esr is so low that there is not enough voltage ramp in the output voltage signal. this fools the error comparator into trig - gering a new cycle immediately after the 400ns minimum off-time period has expired. double-pulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. however, it can indicate the possible presence of loop instability due to insufficient esr. loop instability results in oscillations at the output after line or load steps. such perturbations are usually damped, but can cause the output voltage to rise above or fall below the tolerance limits. the easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output voltage ripple envelope for overshoot and ringing. it can help to simultaneously monitor the inductor current with an ac current probe. do not allow more than one cycle of ringing after the initial step- response under/overshoot. transient response the inductor ripple current also impacts transient- response performance, especially at low v sys - v out differentials. low inductor values allow the inductor cur - rent to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. this favors higher switching-frequency operation. the smpss include an extended on-time feature that reduces the output capacitor requirements due to heavy load transients. the capacitance required is also a func - tion of the maximum duty factor and can be calculated from the following equation: ( ) 2 load(max) out sag out l i k c 2v v d
integrated charger, dual main step-down controllers, and dual ldo regulators MAX17085B 32 _____________________________________________________________________________________ where k is a function of maximum duty cycle (lowest input voltage) and switching frequency as shown in figure 6. the amount of overshoot during a full-load to no-load tran - sient due to stored inductor energy can be calculated as: ( ) 2 load(max) soar out out i l v 2c v d setting the current limit the minimum current-limit threshold must be great enough to support the maximum load current when the current limit is at the minimum tolerance value. the valley of the inductor current occurs at i load(max) minus half the ripple current; therefore: load(max) lim(val) load(max) i lir i i - 2 ? ? > ? ? ? ? ? ? where i lim(val ) equals the minimum valley current-limit threshold voltage divided by the current-sense element (low-side r dson ). connect a resistor-divider from ref to ilim to analog ground (agnd) to set the adjustable current-limit thresh - old. the valley current-limit threshold is approximately 1/10 the ilim voltage over a 0.2v to 2.1v range. the adjustment range corresponds to a 20mv to 210mv val - ley current-limit threshold. when adjusting the current limit, use 1% tolerance resistors to prevent significant inaccuracy in the valley current-limit tolerance. common design procedure the input capacitor and mosfet selection criteria share common considerations for the charger and the main smps. for the following sections, v in is v dcin for the charger and v sys for the main smps, v out is v batt for the charger and v out5 or v out3 for the main smps, and i out is i chg for the charger and i load for the main smps. input capacitor selection the input capacitor must meet the ripple-current require - ment (i rms ) imposed by the switching currents: ( ) out in out rms load in v v - v i i v ? ? ? ? = ? ? ? ? for most applications, nontantalum chemistries (ceramic, aluminum, or os-con) are preferred due to their resis - tance to power-up surge currents typical of systems with a mechanical switch or connector in series with the input. in either configuration, choose a capacitor that has less than 10 n c temperature rise at the rms input current for optimal reliability and lifetime. power-mosfet selection high-side mosfet power dissipation the conduction loss in the high-side mosfet (n h ) is a function of the duty factor, with the worst-case power dissipation occurring at the minimum input voltage, and maximum output voltage in the case of the charger: 2 out ds(on) cond out in v pd (hs) i r v = calculating the switching losses in high-side mosfet (n h ) is difficult since it must allow for difficult quantify - ing factors that influence the turn-on and turn-off times. these factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and pcb layout characteristics. the following switching-loss cal - culation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably includ - ing verification using a thermocouple mounted on n h : 2 g(sw) oss in sw sw in out sw gate q c v f pd (hs) v i f i 2 ? ? = + ? ? ? ? ? ? where c oss is the n h mosfets output capacitance, q g(sw) is the charge needed to turn on the n h mosfet, and i gate is the peak gate-drive source/sink current (2a typ). the following high-side mosfets loss is due to the reverse- recovery charge of the low-side mosfets body diode: figure 6. scale factor vs. duty cycle duty cycle scale factor (k) 0.7 0.8 0.9 1.0 0.6 10 100 1 0.5 800khz 600khz 400khz 200khz
integrated charger, dual main step-down controllers, and dual ldo regulators MAX17085B ______________________________________________________________________________________ 33 rr in sw qrr q v f pd (hs) 2 = the total high-side mosfet power dissipation is: total cond sw qrr pd (hs) pd (hs) pd (hs) pd (hs) + + the optimum high-side mosfet trades the switching losses with the conduction (r ds(on) ) losses over the input and output voltage ranges. for the charger, the losses at v out(min) should be roughly equal to the loss - es at v out(max ) , while for the main smps, the losses at v in(min) should be roughly equal to losses at v in(max) . low-side mosfet power dissipation for the low-side mosfet (n l ), the worst-case power dissipation always occurs at maximum input voltage: 2 out ds(on) cond out in v pd (ls) 1- i r v ? ? = ? ? ? ? the following additional loss occurs in the low-side mosfet due to the body diode conduction losses: bdy peak pd (ls) 0.05i 0.4v = the total power low-side mosfet dissipation is: total cond bdy pd (ls) pd (ls) pd (ls) + mosfet gate drivers (dh, dl) the dh floating high-side mosfet drivers are powered by internal boost switch charge pumps at bst, while the dl synchronous-rectifier drivers are powered directly by the 5v bias supply (v dd ). adaptive dead-time circuits monitor the dl and dh drivers and prevent either fet from turning on until the other is fully off. the adaptive driver dead time allows operation without shoot-through with a wide range of mosfets, minimizing delays and maintaining efficiency. a low-resistance, low-inductance path from the dl and dh drivers to the mosfet gates is used for the adaptive dead-time circuits to work properly; otherwise, the sense circuitry in the MAX17085B interprets the mosfet gates as off while charge actually remains. use very short, wide traces (50 mils to 100 mils wide if the mosfet is 1in from the driver). applications with high-input voltages, long inductive driver trace, and fast rising lx edges may have shoot- through currents when the low-side mosfet gate is pulled up by the mosfets gate-to-drain capacitance (c rss ), gate-to-source capacitance (c iss - c rss ). the following minimum threshold should not be exceeded: rss gs(th) in iss c v v c ? ? > ? ? ? ? typically, adding a 4700pf between dl and power ground (c nl in figure 7), close to the low-side mosfets, greatly reduces coupling. do not exceed 22nf of total gate capacitance to prevent excessive turn-off delays. alternatively, shoot-through currents may be caused by a combination of fast high-side mosfets and slow low- side mosfets. if the turn-off delay time of the low-side mosfet is too long, the high-side mosfets can turn on before the low-side mosfets have actually turned off. adding a resistor less than 5 i in series with b st slows down the high-side mosfet turn-on time, eliminating the shoot-through currents without degrading the turn- off time (r bst in figure 7). slowing down the high-side mosfet also reduces the lx node rise time, thereby reducing emi and high-frequency coupling responsible for switching noise. figure 7. gate-drive circuit MAX17085B n h n l (r bst )* (r bst )* recommended ?the resistor lowers emi by decreasing the switching node rise time. (c nl )* optional?the capacitor reduces lx-to-dl capacitive bst input (v in ) l dh lx ldo5 dl ep c bst (c nl )* c byp coupling that can cause shoot-through currents.
integrated charger, dual main step-down controllers, and dual ldo regulators MAX17085B 34 _____________________________________________________________________________________ boost capacitors the boost capacitors (c bst ) selected must be large enough to handle the gate charging requirements of the high-side mosfets. select the boost capacitors to avoid discharging the capacitor more than 200mv while charg - ing the high-side mosfets gates: gate bst n q c 200mv = where n is the number of high-side mosfets used for one regulator, and q gate is the gate charge specified in the mosfets data sheet. for example, assume (1) fds6298 n-channel mosfets are used on the high side. according to the manufacturers data sheet, a single fds6298 has a maximum gate charge of 19nc (v gs = 5v). using the above equation, the required boost capacitance would be: bst 1 10nc c 0.05 f 200mv = = f selecting the closest standard value, this example requires a 0.1 f f ceramic capacitor. applications information setting charger input current limit the input current limit should be set based on the cur - rent capability of the ac adapter and the tolerance of the input current limit. the upper limit of the input current threshold should never exceed the adapters minimum available output current. for example, if the adapters output current rating is 5a p 10%, the input current limit should be selected so that its upper limit is less than 5a x 0.9 = 4.5a. since the input current-limit accuracy of the MAX17085B is p 2%, the typical value of the input cur - rent limit should be set at 4.5a divided by 1.02 4.41a. the lower limit for input current must also be considered. for chargers at the low end of the specification, the input current limit for this example could be 4.41a x 0.95 or approximately 4.19a. ac adapter detection the minimum adapter voltage threshold is used to calcu - late the resistor values at acin: acin2 adp(min) acin-acok acin1 acin2 r v v r r = + where v acin-acok is 1.5v (typ). to minimize power loss, choose a large value for r acin1 , and calculate r acin2 . for example: v adp(min) = 17v r acin1 = 249k i then: ( ) acin1 acin2 adp(min) acin - acok r r 24.1k v v - 1 = = ? the nearest standard resistor value for r acin2 is 24.3k i . the acov threshold is then determined by: acin1 adp(ov) acin-acov acin2 r v v 1 r ? ? = + ? ? ? ? where v acin-acov is 2.1v (typ). using the values in the example above, v adp(ov) is 23.7v. relearn application the relearn function is easily implemented in the MAX17085B by configuring the system to override the pdsl gate drive to the adapter and battery selector mosfets as shown in figure 1. the system initiates the relearn cycle by disabling the adapter selector mosfet and enabling the battery selector mosfet. the MAX17085B relies on the system to monitor the battery discharge voltage. when the battery reaches its critical discharge voltage threshold, the system reenables the adapter selector mosfet. important: keep iset low during the relearn cycle. when the relearn cycle is completed, release pdsl first, wait 10ms, then enable charging. main smps dropout performance the output voltage for continuous-conduction opera - tion is restricted by the nonadjustable minimum off-time one-shot. for best dropout performance, use the slower (200khz) on-time setting. when working with low input voltages, the duty-factor limit must be calculated using worst-case values for on- and off-times. also, keep in mind that transient response performance of buck regulators operated too close to dropout is poor, and bulk output capacitance must often be added (see the design procedure section). the absolute point of dropout is when the inductor current ramps down during the minimum off-time ( d i down ) as much as it ramps up during the on-time ( d i up ). the ratio h = d i up / d i down indicates the controllers ability to slew the inductor current higher in response to increased load, and must always be greater than 1. as h approaches 1, the absolute minimum dropout point, the inductor current cannot increase as much during each switching cycle, and v sag greatly increases unless additional output capacitance is used.
integrated charger, dual main step-down controllers, and dual ldo regulators MAX17085B ______________________________________________________________________________________ 35 a reasonable minimum value for h is 1.5 for most normal regulators. with the extended on-time feature, the mini - mum h value of 1 can be used. adjusting this up or down allows trade-offs between v sag , output capacitance, and minimum operating voltage. for a given value of h, the minimum operating voltage can be calculated as: out chg in(min) off(min) sw v v v h t 1- t + = ? ? ? ? ? ? where v chg is the parasitic voltage drop in the charge path (see the on-time one-shot section) and t off(min) is from the electrical characteristics . if the calculated v in(min) is greater than the required minimum input voltage, then operating frequency must be reduced or output capacitance added to obtain an acceptable v sag . if operation near dropout is anticipated, calculate v sag to be sure of adequate transient response. dropout design example: v out = 5v, f sw = 600khz, t sw = 1.67 f s, t off(min) = 250ns, v chg = 100mv, h = 1: in(min) 5v 0.1v v 6v 1 250ns 1- 1.67 s + = = ? ? ? ? ? ? f therefore, v in must be greater than 6v for steady-state operation. input transient sags down to 5.5v during an output load transient are acceptable due to the extended on-time feature. charge pump the MAX17085B provides a simple way to generate and valley regulate an auxiliary charge pump to provide a low-power, high-voltage (12v to 15v) supply for load switch gate drive bias. figure 8 shows the charge-pump application circuit. the charge pump is driven by the dl pin to boost the output to the desired bias voltage (v chg-pump ): chg - pump f v 3 (5v - v ) where v f is the forward voltage drop of the diodes. connect a resistor-divider from the high-voltage output to the skip pin as shown in figure 8. when the voltage at the skip pin drops to 2.1v, which is the typical falling- edge threshold between skip mode and forced-pwm mode, the MAX17085B enters forced-pwm operation, recharging the bias output. this automatic refresh opera - tion allows the MAX17085B to remain in skip mode for best efficiency, yet keep the charge pump output above a minimum threshold. the minimum charge-pump volt - age is: chg-pump(min) r1 v 2.1v 1 r2 ? ? = + ? ? ? ? pcb layout guidelines careful pcb layout is critical to achieving low switching losses and clean, stable operation. the switching power stage requires particular attention. if possible, mount all the power components on the top side of the board, with their ground terminals flush against one another. follow these guidelines for good pcb layout: u keep the high-current paths short, especially at the ground terminals. this practice is essential for stable, jitter-free operation. u keep the power traces and load connections short and wide. this practice is essential for high efficiency. using thick copper pcbs (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. correctly routing pcb traces is a difficult task that must be approached in terms of fractions of centimeters, where a single milliohm of excess trace resistance causes a measur - able efficiency penalty. figure 8. charge-pump application 5v output n h5 n l5 d x1 d x2 c1 10nf c4 0.1ff c out5 c bst5 0.1ff dh5 bst5 dl5 lx5 l5 out5 12v to 15v charge pump skip c2 0.1ff MAX17085B c3 10nf r1 100ki r2 21ki
integrated charger, dual main step-down controllers, and dual ldo regulators MAX17085B 36 _____________________________________________________________________________________ u minimize the main smps current-sensing errors by connecting lx3 and lx5 directly to the drain of the low-side mosfet. minimize the charger current- sense resistor trace lengths, and ensure accurate current sensing with kelvin connections. u when trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to be made longer than the discharge path. for example, it is better to allow some extra distance between the input capacitors and the high-side mosfet than to allow distance between the inductor and the low-side mosfet or between the inductor and the output filter capacitor. u route high-speed switching nodes (bst_, lx_, dh_, and dl_) away from sensitive analog areas (ref, vcc, and out). u refer to the MAX17085B evaluation kit for the layout example. layout procedure 1) place the power components first, with ground termi - nals adjacent (nl_ source, cin, and cout). if pos - sible, make all these connections on the top layer with wide, copper-filled areas. 2) mount the controller ic adjacent to the low-side mosfet, preferably on the backside opposite nl_ and nh_ to keep lx_, gnd, dh_, and the dl_ gate- drive lines short and wide. the dl_ and dh_ gate traces must be short and wide (50 mils to 100 mils wide if the mosfet is 1in from the controller ic) to keep the driver impedance low and for proper adap - tive dead-time sensing. 3) group the gate-drive components (bst_ capacitor, ldo5 bypass capacitor) together near the controller ic. 4) make the dc-dc controller ground connections as shown in figure 1. this diagram can be viewed as having two separate ground planes: power ground, where all the high-power components go, and an ana - log ground plane for sensitive analog components. the analog ground plane and power ground plane must meet only at a single point directly at the ic. 5) connect the output power planes directly to the out - put filter capacitor positive and negative terminals with multiple vias. place the entire dc-dc converter circuit as close to the load as is practical. 6) use a single-point star ground placed directly below the part at the pgnd pin. connect the power ground (ground plane) and the quiet ground island at this location.
integrated charger, dual main step-down controllers, and dual ldo regulators MAX17085B maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 37 ? 2010 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. chip information process: bicmos package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code document no. 40 tqfn-ep t4055-2 21-0140 pin configuration MAX17085B thin qfn top view 35 36 34 33 12 11 13 bst3 out3 ldo3 dcin ldo5 14 lx3 cc iinp cssp acin vctl v cc cssn pdsl 1 2 + ilim3 4 5 6 7 27 28 29 30 26 24 23 22 ilim5 skip acok pgood dhc lxc dl3 cells 3 25 37 ton bstc 38 39 40 on3 on5 dh3 dlc dh5 lx5 gnd 32 15 csin ref 31 16 17 18 19 20 csip out5 dl5 bst5 batt 8 9 10 21 iset

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